THEORY Number systems - Basic Theorems and Properties of Boolean Algebra - Minimization of Boolean expressions- Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization, completely and incompletely specified functions Quine- Mc Cluskey method, Logic Gates, Implementation of Boolean expressions using universal gates. PRACTICAL 1.Verification of Logic Gates. 2.Design and implementation of Boolean logic functions using universal gates. 3.Implementation of binary adder and subtractor using logic gates.

THEORY Design procedure –Adder –Subtractor – Multiplexer - Demultiplexer – decoder - encoder – code converters: Binary to Gray, Gray to binary, BCD to Excess 3, Excess 3 to BCD – Magnitude Comparator - Parity Generator/Checker,. Case study: Digital trans-receiver / 8 bit Arithmetic and logic unit, Seven Segment display decoder PRACTICAL 1.Design and implementation of code converters using logic gates. 2.Design and implementation of multiplexer/demultiplexer using logic gates. 3.Design and implementation of Parity Generator/Checker using logic gates.

THEORY Latches – Fundamentals of SR, JK, T, D and Master/Slave FF: Operation and excitation tables, Analysis and design of clocked sequential circuits –Finite State Machines - Moore/Mealy models, state minimization, state assignment. Hazards, Essential Hazards, Design of Hazard free circuits. PRACTICAL 1.Implementation of T flip-flop using JK flip-flop 2.Implementation of JK flip-flop using SR flip-flop

THEORY Registers: Shift registers – SISO,SIPO,PISO,PIPO, Universal shift register. Counters: Ripple counters - Synchronous counters - up/down counter - Modulo–n counter- Decade counters - Ring counters. PRACTICAL 1.Implementation of shift registers using Flip- flops. 2.Design and implementation of synchronous counter. 3.Design and implementation of Ring counter.

THEORY Programmable Logic Devices: PROM,Programmable Logic Array (PLA), Programmable Array Logic (PAL), Implementation of combinational logic using PROM, PLA and PAL Digital logic families: TTL, ECL and CMOS - Implementation of combinational circuits using Verilog Hardware Description Language. PRACTICAL 1.Simulation of adder/subtractor using Verilog Hardware Description Language. Simulation of shift register using Verilog Hardware Description Language.